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| 1 ? fn6381.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. isl8700a, isl8701a, isl8702a, isl8703a, isl8704a, isl8705a adjustable quad sequencer the isl8700a, isl8701a, isl8702a, isl8703a, isl8704a, isl8705a family of ics provide four delay adjustable sequenced outputs while monitoring an input voltage all with a minimum of external components. high performance dsp, fpga, p and various sub-systems require input power sequencing for proper functionality at initial power up and the isl870xa provides this function while monitoring the distributed voltage for over and undervoltage compliance. these ics operate over the +3.3v to +24v nominal voltage range. all have a user adjustable time from uv and ov voltage compliance to sequencing start via an external capacitor when in auto start mode and adjustable time delay to subsequent enable output signal via external resistors. additionally, the isl8702a, isl8703a, isl8704a and isl8705a provide i/o for sequencing on and off operation (seq_en) and for voltage window compliance reporting (fault) over the +3.3v to +24v nominal voltage range. easily daisy chained for more than 4 sequenced signals. altogether, the isl870xa provides these adjustable features with a minimum of external bom. see figure 1 for typical implementation. features ? adjustable delay to subsequent enable signal ? adjustable delay to sequence auto start ? adjustable distributed voltage monitoring ? under and overvoltage adjustable delay to auto start sequence ? i/o options enable (isl8700a, isl8702a, isl8704a) and enable# (isl8701a, isl8703a, isl8705a) seq_en (isl8702a, isl8703a) and seq_en# (isl8704a, isl8705a) ? voltage compliance fault output ? pb-free plus anneal available (rohs compliant) applications ? power supply sequencing ? system timing function pinout isl870xa (14 ld soic) top view ordering information part number (note 1) part marking temp. range (c) package (pb-free) pkg. dwg. # isl8700aibz* isl8700aibz -40 to +85 14 ld soic m14.15 ISL8701AIBZ* ISL8701AIBZ -40 to +85 14 ld soic m14.15 isl8702aibz* isl8702aibz -40 to +85 14 ld soic m14.15 isl8703aibz* isl8703aibz -40 to +85 14 ld soic m14.15 isl8704aibz* isl8704aibz -40 to +85 14 ld soic m14.15 isl8705aibz* isl8705aibz -40 to +85 14 ld soic m14.15 isl870xaeval1 evaluation platform *add ?-t? suffix for tape and reel. notes: 1. intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. enable_d enable_c enable_b enable_a 1 2 3 4 5 vin td tc tb 6 7 8 9 14 time seq_en (nc on isl8700a/01a) fault (nc on isl8700a/01a) ov uv gnd 13 12 11 10 isl8701a, isl8703a, isl8705a pins 1-4 are enable# function isl8704a, isl8705a pin 9 is seq_en# function enable_a uv ov gnd tb tc td time vin fault * seq_en * enable_b enable_c enable_d 3.3-24v dc/dc en dc/dc en dc/dc en dc/dc en vo1 vo2 vo3 v04 figure 1. isl870xa implementation * seq_en and fault are not available on isl8700a and isl8701a ru rm rl data sheet october 12, 2006
2 fn6381.0 october 12, 2006 absolute maximum rati ngs thermal information v in , enable(#), fault . . . . . . . . . . . . . . . . . . . . . . . 27v, to -0.3v time, tb, tc, td, uv, ov . . . . . . . . . . . . . . . . . . . . . +6v, to -0.3v seq_en(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v in +0.3v, to -0.3v enable, enable # output current . . . . . . . . . . . . . . . . . . . 10ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage range (nominal). . . . . . . . . . . . . . . . . . 3.3v to 24v thermal resistance (typical, note 2) ja (c/w) 14 ld soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 maximum junction temperature (plastic package) . . . . . . . +125c maximum storage temperature range . . . . . . . . . .-65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300c (soic lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 2. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications nominal v in = 3.3v to +24v, t a = t j = -40c to+85c, unless otherwise specified. parameter symbol test conditions min typ max unit uv and ov inputs uv/ov rising threshold v uvrvth 1.16 1.21 1.28 v uv/ov falling threshold v uvfvth 1.06 1.10 1.18 v uv/ov hysteresis v uvhys v uvrvth - v uvfvth -104-mv uv/ov input current i uv -10-na time, enable/enable# outputs time pin charging current i time -2.6- a time pin threshold v time_vth 1.9 2.0 2.25 v time from v in valid to enable_a t vinseqpd seq_en = high, c time = open - 30 - s t vinseqpd_10 seq_en = high, c time = 10nf - 7.7 - ms t vinseqpd500 seq_en = high, c time = 500nf - 435 - ms time from v in invalid to shutdown t shutdown uv or ov to simultaneous shutdown - - 1 s enable output resistance r en i enable = 1ma - 100 - enable output low vol i enable = 1ma - 0.1 - v enable pull-down current i pulld enable = 1v 10 15 - ma delay to subsequent enable turn-on/off t del_120 r tx = 120k 155 195 240 ms t del_3 r tx = 3k 3.5 4.7 6 ms t del_0 r tx = 0 -0.5-ms sequence enable and fault i/o v in valid to fault low t fltl 15 30 50 s v in invalid to fault high t flth -0.5- s fault pull-down current fault = 1v 10 15 - ma seq_en pull-up voltage v seq seq_en open - 2.4 - v seq_en low threshold voltage vil seq_en --0.3v seq_en high threshold voltage vih seq_en 1.2 - - v delay to enable_a deasserted t seq_en_ena seq_en low to enable_a low - 0.2 1 s bias ic supply current i vin_3.3v v in = 3.3v - 191 - a i vin_12v v in = 12v - 246 400 a i vin_24v v in = 24v - 286 - a v in power on reset v in_por v in low to high - 2.3 2.8 v isl8700a, isl8701a, isl8702a , isl8703a, isl8704a, isl8705a 3 fn6381.0 october 12, 2006 pin descriptions pins pin name function description 8700a 8701a 8702a 8703a 8704a 8705a na 1 na 1 na 1 enable#_d active low open drain sequenced output. sequenced on after enable#_c and first output to sequence off for the isl870 1a, isl8703a, isl8705a. tracks v in upon bias. 1 na 1 na 1 na enable_d active high open drain sequenced output. sequenced on after enable_c and first output to sequence off for the isl8700a, isl8702a, isl8704a. pulls low with v in < 1v. na 2 na 2 na 2 enable#_c active low open drain sequenced output. sequenced on after enable#_b and sequenced off after enable#_d for the isl870 1a, isl8703a, isl8705a. tracks v in upon bias. 2 na 2 na 2 na enable_c active high open drain sequenced output. sequenced on after enable_b and sequenced off after enable_d for the isl8700a, isl8702a, isl8704a. pulls low with v in < 1v. na 3 na 3 na 3 enable#_b active low open drain sequenced output. sequenced on after enable#_a and sequenced off after enable#_c for the isl870 1a, isl8703a, isl8705a. tracks v in upon bias. 3 na 3 na 3 na enable_b active high open drain sequenced output. sequenced on after enable_a and sequenced off after enable_c for the isl8700a, isl8702a, isl8704a. pulls low with v in < 1v. na 4 na 4 na 4 enable#_a active low open drain sequenced output. sequenced on after ctime period and sequenced off after enable#_b fo r the isl8701a, isl8703a, isl8705a. tracks v in upon bias. 4 na 4 na 4 na enable_a active high open drain sequenced output. sequenced on after ctime period and sequenced off after enable_b for the isl8700a, isl8702a, isl8704a. pulls low with v in < 1v. 5 5 5 5 5 5 ov the voltage on this pin mu st be under its 1.22v vth or the four en able outputs will be immediately pulled down. conversely the 4 enable# outputs will be released to be pulled high via external pull-ups. 6 6 6 6 6 6 uv the voltage on this pin must be over it s 1.22v vth or the four enable outputs will be immediately pulled down. conversely the 4 enable# outputs will be released to be pulled high via external pull-ups. 777777 gndic ground. na na 8 8 8 8 fault the v in voltage when not within the desired uv to ov window will cause fault to be released to be pulled high to a voltage equal to or less than v in via an external resistor. na na 9 9 na na seq_en this pin provides a sequence on signal input with a high input. internally pulled high to ~2.4v. na na na na 9 9 seq_en# this pin provides a sequence on signal input with a low input. internally pulled high to ~2.4v. 10 10 10 10 10 10 time this pin provides a 2.6a current output so that an adjustable v in valid to sequencing on and off start delay period is created with a capacitor to ground. 11 11 11 11 11 11 tb a resistor connected from this pin to ground determines the time delay from enable_a being active to enable _b being active on turn-on and also going inactive on turn-off via the seq_in input. 12 12 12 12 12 12 tc a resistor connected from this pin to ground determines the time delay from enable_b being active to enable _c being active on turn-on and also going inactive on turn-off via the seq_in input. 13 13 13 13 13 13 td a resistor connected from this pin to ground determines the time delay from enable_c being active to enable _d being active on turn-on and also going inactive on turn-off via the seq_in input. 14 14 14 14 14 14 v in ic bias pin nominally 3.3v to 24v this pin requires a 1 f decoupling capacito r close to ic pin. isl8700a, isl8701a, isl8702a , isl8703a, isl8704a, isl8705a 4 fn6381.0 october 12, 2006 functional block diagram functional description the isl870xa family of ics provides four delay adjustable sequenced outputs while monitoring a single distributed voltage in the nominal range of 3.3v to 24v for both under and overvoltage. only when the voltage is in compliance will the isl870xa initiate the pre-prog rammed a-b-c-d sequence of the enable (isl8700a, isl8702a, isl8704a) or enable# (isl8701a, isl8703a, isl8705a) outputs. although this ic has a bias range of 3.3v to 24v it can monitor any voltage >1.22v via the external divider if a su itable bias voltage is otherwise provided. during initial bias voltage (v in ) application the isl8700a, isl8702a, isl8704a enable outputs are held low once v in = 1v whereas the isl8701a, isl8703a, isl8705a enable# outputs follow the rising v in . once v in > the v bias power on reset threshold (por) of 2.8v, v in is constantly monitored for compliance via the input voltage resistor divider and the voltages on the uv and ov pins and reported by the fault output. internally, voltage regulators generate 3.5v and 1.17v 5% voltage rails for internal usage once v in > por. once uv > 1.22v and with the seq_en pin high or open, (seq_en# must be pulled low on isl8704a, isl8705a) the auto sequence of the four enabl e (enable#) outputs begins as the time pin charges its external capacitor with a 2.6a current source. the voltage on time is compared to the internal reference (v time_vth ) comparator input and when greater than v time_vth the isl8700a, isl8702a, isl8704a enable_a is released to go high via an external pull-up resistor or a pull-up in a dc/dc convertor enable input, for example. conversely, enable#_a output will be pulled low at this time on an isl8701a, isl8703a, isl8705a. the time delay generated by the external capacitor is to assure continued voltage compliance within the programmed limits, as during this time any ov or uv condition will halt the start-up process. time cap is discharged once v time_vth is met. once enable_a is active (either released high on the isl8700a, isl8702a, isl8704a or pulled low, isl8701a, isl8703a, isl8705a) a counter is started and using the resistor on tb as a timing component a delay is generated before enable_b is activated. at this time, the counter is restarted using the resistor on tc as its timing component for a separate timed delay until enable_c is activated. this process is repeated for the resistor on td to complete the a-b-c-d sequencing order of the enable or enable# outputs. at any time during sequencing if an ov or uv event is registered, all four enable outputs will immediately return to their reset state; low for isl8700a, isl8702a, isl8704a and high for isl8701a, isl8703a, isl8705a. c time is immediately discharged after initial ramp up thus waiting for subsequent voltage compliance to restart. once sequencing is complete, any subsequently regi stered uv or ov event will trigger an immediate and simultaneous reset of all enable or enable# outputs. vin voltage 1.17v internal voltage regulator vin (2.8v min - 27v max) 2.0v vin por 3.5v logic vin programmable delay timer v time_vth 2.6 a vin tb tc td enable_a enable_b enable_c enable_d time gnd fault seq_en uv ov + - - + eo vref 30 s reference isl8700a, isl8701a, isl8702a , isl8703a, isl8704a, isl8705a 5 fn6381.0 october 12, 2006 on the isl8702a, isl8703a, isl8704a and isl8705a, enabling of on or off sequencing can also be signaled via the seq_en or seq_en# input pin once voltage compliance is met. initially, the seq_en pin should be held low and released when sequence star t is desired. the seq# is internally pulled high and sequencing is enabled when it is pulled low. the on sequence of the enable outputs is as previously described. the of f sequence feature is only available on the variants having the seq_en or the seq_en# inputs, these being the isl8702a, isl8703a, isl8704a, isl8705a. the sequence is d off, then c off, then b off and finally a off. once seq_en (seq_en#) is signaled low (high), the time cap is char ged to 2v once again. once this vth is reached, enable_d transitions to its reset state and ctim is discharged. a delay and subsequent sequence off is then determined by td re sistor to enable_c. likewise, a delay to enable_b and then enable_a turn-off is determined by tc and tb resistor values respectively. with the isl8700a, isl8701a a quasi down sequencing of the enable outputs can be achieved by loading the enable pins with various value capacitors to ground. when a simultaneous output latch off is invoked, the caps will set the falling ramp of the various enable outputs thus adjusting the time to vth for various dc/dc convertors or other circuitry. regardless of ic variant, the fault signal is always valid at operational voltages and can be used as justification for seq_en release or even controlled with an rc timer for sequence on. programming the under and overvoltage limits when choosing resistors for the divider remember to keep the current through the string bounded by power loss at the top end and noise immunity at the bott om end. for most applications, total divider resistance in the 10k to1000k range is advisable with high precision resistors being used to reduce monitoring error. although for the isl870xa, two dividers of two resistors each can be employed to separately monitor the ov and uv levels for the v in voltage. we will discuss using a single three resistor string for monitoring the v in voltage, referencing figure 1. in the three resistor divider string with ru (upper), rm (middle) and rl (lower), the ratios of each in combination to the other two is balanced to achieve the desired uv and ov trip levels. although th is ic has a bias range of 3.3v to 24v, it can monitor any voltage >1.22v. the ratio of the desired overvolt age trip point to the internal reference is equal to the ratio of the two upper resistors to the lowest (gnd connected) resistor. the ratio of the desired undervoltage trip point to the internal reference voltage is equal to the ratio of the uppermost (voltage connected) resistor to the lower two resistors. these assumptions are true for both rising (turn-on) or falling (shutdown) voltages. the following is a practical example worked out. for detailed equatons on how to perform this operation for a given supply requirement please see the next section. 1. determine if turn-on or shutdown limits are preferred. in this example, we will determine the re sistor values based on the shutdown limits. 2. establish lower and upper trip level: 12v 10% or 13.2v (ov) and 10.8v (uv) 3. establish total resistor string value: 100k , ir = divider current 4. (rm+rl) x ir = 1.1v @ uv and rl x ir = 1.2v @ ov 5. rm+rl = 1.1v/ir @ uv = rm+rl = 1.1v/(10.8v/100k ) = 10.370k 6. rl = 1.2v/ir @ ov = rl = 1.2v/(13.2v/100k ) = 9.242k 7. rm = 10.370k - 9.242k = 1.128k 8. ru = 100k - 10.370k = 89.630k 9. choose standard value resistors that most closely approximate these ideal values . choosing a different total divider resistance value may yield a more ideal ratio with available resistor?s values . in our example, with the closest standard values of ru = 90.9k , rm = 1.13k and rl = 9.31k , the nominal uv falling and ov rising will be at 10.9v and 13.3v respectively. programming the e nable output delays the delay timing between the four sequenced enable outputs are programmed with four external passive components. the delay from a valid v in (isl8700a and isl8701a) to enable_a and seq_en being valid (isl8702a, isl8703a, isl8704a, isl8705a) to enable_a is determined by the value of the capacitor on the time pin to gnd. the external time pin capacitor is charged with a 2.6a current source. once the voltage on time is charged up to the internal reference voltage, (v time_vth ) the enable_a output is released out of its reset state. the capacitor value for a desired delay (10%) to enable_a once v in and seq_en where applicable has been satisfied is determined by: c time = t vinseqpd /770k once enable_a reaches v time_vth , the time pin is pulled low in preparation for a sequenced off signal via seq_en. at this time, the sequencing of the subsequent outputs is started. enable_b is released out of reset after a programmable time, then enable_c, then enable _d, all with their own programmed delay times. the subsequent delay times are programmed with a single external resistor for each enable output providing maximum flexibility to the designer through th e choice of the resistor value connected from tb, tc and td pins to gnd. the resistor values determine the charge and discharge rate of an internal capacitor comprising an rc time constant for an oscillator whose output is fed into a counter generating the timing delay to enable output sequencing. the r tx value for a given delay time is defined as: r tx = t del /1667nf isl8700a, isl8701a, isl8702a , isl8703a, isl8704a, isl8705a 6 fn6381.0 october 12, 2006 an advanced tutorial on setting uv and ov levels this section discusses in additional detail the nuances of setting the uv and ov levels, providing more insight into the isl870xa than the earlier text. the following equation set can alternatively be used to work out ideal values for a 3 resistor divider string of ru, rm and rl. these equations assume that v ref is the center point between v uvrvth and v uvfvth (i.e. (v uvrvth + v uvfvth )/2 = 1.17v), iload is the load current in the resistor string (i.e. v in /(ru + rm + rl)), v in is the nominal input voltage and vtol is the acceptable voltage tolerance, such that the uv and ov thresholds are centered at v in vtol. the actual acceptable voltage window will also be affected by the hysteresis at the uv and ov pins. this hysteresis is amplified by the resistor string such that the hysteresis at the top of the string is: vhys = v uvhys x v out /v ref this means that the v in vtol thresholds will exhibit hysteresis resulting in thresholds of v in + vtol vhys/2 and v in - vtol vhys/2. there is a window between the v in rising uv threshold and the v in falling ov threshold where the input level is guaranteed not to be detected as a fault. this window exists between the limits v in (vtol - vhys/2). there is an extension of this window in each direction up to v in (vtol + vhys/2), where the voltage may or may not be detected as a fault, depending on the direction from which it is approached. these two equations may be used to determine the required value of vtol for a given system. for example, if v in is 12v, vhys = (0.1 x 12)/1.17 = 1.03v. if v in must remain within 12v 1.5v, vtol = 1.5 - 1.03/2 = 0.99v. this will give a window of 12 0.48v where the system is guaranteed not to be in fault and a limit of 12 1.5v beyond which the system is guaran teed to be in fault. it is wise to check both these voltages, for if the latter is made to tight, the former will cease to exist. this point comes when vtol < vhys/2 and results from the fact that the acceptable window for the ov pin no longer aligns with the acceptable window for the uv pin. in this case, the application will have to be changed such that uv and ov are provided separate resistor strings. in this case, the uv and ov thresholds can be individually controlled by adjusting the relevant divider. the previous example will give voltage thresholds of: with v in rising uvr = v in - vtol + vhys/2 = 11.5v and ovr = v in + vtol + vhys/2 = 13.5v with v in falling ovf = v in + vtol - vhys/2 = 12.5v and uvf = v in - vtol - vhys/2 = 10.5v. so with a single three resistor st ring, the resistor values can be calculated as: rl = (v ref /iload) (1 - vtol/v in ) rm = 2(v ref x vtol)/(v in x iload) ru = 1/iload x (v in - v ref (1+vtol/v in )) for the above example, with vtol = 0.99v, assuming a 100a iload at v in = 12v: rl = 10.7k rm = 1.9k ru = 107.3k figure 2. isl8702a operational diagram enable outputs abcd fault a b c d seq_en time isl8700a, isl8701a, isl8702a , isl8703a, isl8704a, isl8705a 7 fn6381.0 october 12, 2006 applications usage using the isl870xaeval1 platform the isl870xaeval1 platform is the primary evaluation board for this family of sequencers. see figure 16 for photograph and schematic.the evaluation board is shipped with an isl8702a mounted in the left position and with the other device variants loose packed. in the following discussion, test points names are bold on initial occurrence for identification. the v in test point is the chip bias and can be biased from 3.3v to 24v. the vhi test point is for the enable and fault pull-up voltage which are limited to a maximum of 24v independent of v in . the uv/ov resistor divider is set so that a nominal 12v on the vmonitor test point is compliant and with a rising ov set at 13.2v and a falling uv set at 10.7v. these three test points (v in ,vhi and vmonitor) are brought out separately for maximum flexibility in evaluation. vmonitor ramping up and down through the uv and ov levels will result in the fault output signaling the out of bound conditions by being released to pull high to the vhi voltage as shown in figures 6 and 7. once the voltage monitoring fault is resolved and where applicable, the seq_en (#) is satisfied, sequencing of the enable_x(#) outputs begins. when sequence enabled the enable_a , enable_b , enable_c and lastly enable_d are asserted in that order and when seq_en is disabled the order is reversed. see figures 8 and 9 demonstrating the sequenced enabling and disabling of the enable outputs. the timing between enable outputs is set by the resistor values on the tb, tc, td pins as shown. figure 10 illustrates the timing from either seq_en and/or vmonitor being valid to enable_a being asserted with a 10nf time capacitor. figure 11 shows that enable_x outputs are pulled low even before v in = 1v. this is critical to ensure that a false enable is not signaled. figure 12 illustrates the seq_en# input disabling and enabling the isl8705a enable# outputs. notice the reversal in order and delay timing from enable_x# to enable_x#. figure 13 shows the time from seq_en transition with the voltage ramping across the ti me capacitor to time vth being met. this results in the immediate pull down of the time pin and simultaneous enable_a enabling. figure 3. isl8702a, isl8703a, isl8704a, isl8705a fault operational diagram undervoltage overvoltage monitored voltage fault output t flth limit limit ramping up and down t flth t fltl t fltl 9 fn6381.0 october 12, 2006 figure 12. isl8705a enable_x# to enable_x# figure 13. seq_en to enable_a figure 14. ov and uv transient immunity seq_en# enable_a# enable_b# enable_c# enable_d# enable_a time seq_en 0.5v/div 8s/div fault = low vmonitor ov vmonitor uv isl8700a, isl8701a, isl8702a , isl8703a, isl8704a, isl8705a 10 fn6381.0 october 12, 2006 application recommendations best practices v in decoupling is required, a 1 f capacitor is recommended. coupling from the enable_x pins to the sensitive uv and ov pins can cause false ov/uv events to be detected. this is most relevant for isl8700a, isl8702a, isl8704a parts due to the enablea and ov pins being adjacent. this coupling can be reduced by adding a ground trace between uv and the enable/fault signals, as shown in figure 15. the pcb traces on ov and uv should be kept as small as practical and the enable_x and fault traces should ideally not be routed under/over the ov/uv traces on different pcb layers unless there is a ground or power plane in between. other methods that can be used to eliminate this issue are by reducing the valu e of the resistors in the network connected to uv and ov (r2, r3, r5 in figure 16) or by adding small decoupling capacitors to ov and uv (c2 and c7 in figure 16). both these methods act to reduce the ac impedance at the nodes, alt hough the latter method acts to filter the signals which will also cause an increase in the time that a uv/ov fault takes to be detected . when the isl870xa is implemented on a hot swappable card that is plugged into an always powered passive back plane an rc filter is required on the v in pin to prevent a high dv/dt transient. with the already existing 1 f decoupling capacitor the addition of a small series r (>50 ) to provide a time constant >50 s is all that is necessary. figure 15. layout detail of gnd between pins 4 and 5 pin 4 pin 5 gnd isl8700a, isl8701a, isl8702a , isl8703a, isl8704a, isl8705a 11 fn6381.0 october 12, 2006 . figure 16. isl870xaeval1 photograp h and schematic of left channel timing components resistors uv/ov set resistors pull-up table 1. isl870xaeval1 left channel component listing component designator component functi on component description u1 isl8702a , quad under/overvolta ge sequencer intersil, isl8702a , quad under/overvoltage sequencer r3 uv resistor for divider string 1.1k 1%, 0603 r2 vmonitor resistor for divider string 88.7k 1%, 0603 r5 ov resistor for divider string 9.1k 1%, 0603 c1 c time sets delay from sequence start to first enable 0.01 f, 0603 r1 r td sets delay from third to fourth enable 120k 1%, 0603 r9 r tb sets delay from first to second enable 3.01k 1%, 0603 r7 r tc sets delay from second to third enable 51k 1%, 0603 r4, r6, r8, r10, r11 enable_x(#) and fault pull-up resistors 4k 10%, 0402 c3 decoupling capacitor 1 f, 0603 isl8700a, isl8701a, isl8702a , isl8703a, isl8704a, isl8705a 12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6381.0 october 12, 2006 isl8700a, isl8701a, isl8702a , isl8703a, isl8704a, isl8705a small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not ex ceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93 |
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